S9S12G240F0MLH belongs to 16-bit MCU of NXP electronic components.Ports P, J and AD offer pin interrupt capability. The related interrupt enable (PIE) as well as the sensitivity to rising or falling edges (PPS) can be individually configured on per-pin basis. All bits/pins in a port share the same interrupt vector. Interrupts can be used with the pins configured as inputs or outputs.
If more than one output signal is attempted to be enabled on a specific pin, a priority scheme determines the signal taking effect.
General rules:
-The peripheral with the highest amount of pins has priority on the related pins when it is enabled.
-If a peripheral can selectively disable a function, the freed up pin is used with the next enabled peripheral signal.
-The general-purpose output function takes control if no peripheral function is enabled.
S9S12G240F0MLH NXP Electronic Components Features
Type
Main product features
S9S12G240F0MLH
Control register for free-running clock outputs
Data registers and data direction registers for ports A, B, C, D, E, T, S, M, P, J and AD when used as general-purpose I/O
Control registers to enable/disable pull devices and select pullups/pulldowns on ports T, S, M, P, J and AD on per-pin basis
Single control register to enable/disable pull devices on ports A, B, C, D and E, on per-port basis and on BKGD pin
Keyword: chip resistor
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